Процессор для ноутбука Intel Core i5-480M Processor (3M Cache, 2.667 GHz) SLC27 Frequency in IDA mode (GHz) 2.933

General information
Type	CPU / Microprocessor
Family	Intel Core i5 Mobile
Processor number ?	i5-480M
Part number	CP80617005487AC
Frequency (GHz) ?	2.667
Frequency in IDA mode (GHz)	2.933
Clock multiplier ?	20
Package type	988-pin micro-FCPGA
Socket type	Socket G1 (rPGA988A)
Architecture / Microarchitecture / Other
Core stepping	K0
Processor core	Arrandale
Manufacturing technology (micron)	0.032
Number of cores	2
L2 cache size (KB) ?	512
L3 cache size (MB)	3
Features	EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? Hyper-Threading technology MMX SSE SSE2 SSE3 SSE4 SSSE3 Turbo Boost technology Virtualization technology (VT-x)
Case temperature (°C) ?	105
Thermal Design Power (Watt) ?	35
Notes on sSpec SLC27
The part supports DDR3-1066 and DDR3-800 memory. Direct Memory Interface speed is 2.5 GT/s. Frequency of integrated graphics controller in turbo mode is 766 MHz. Integrated graphics controller runs at 500 MHz.

SLC27 CPUID information

Intel Core i5 Mobile i5-480M SLC27

Part number:	CP80617005487AC
Measured Frequency:	2659 MHz

Comment:
Submitted by:	CPU-World

General information

Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz
Cores:	2
Logical processors:	4
Processor type:	Original OEM Processor
CPUID signature:	20655
Family:	6 (06h)
Model:	37 (025h)
Stepping:	5 (05h)
TLB/Cache details:	64-byte Prefetching Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries Instruction TLB: 4-KB pages, 4-way set associative, 64 entries Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache details

Cache:	L1 data	L1 instruction	L2	L3
Size:	2 x 32 KB	2 x 32 KB	2 x 256 KB	3 MB
Associativity:	8-way set associative	4-way set associative	8-way set associative	12-way set associative
Line size:	64 bytes	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped	Inclusive Direct-mapped Shared between all cores

Supported instructions

Integrated features and technologies

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Hyper-Threading Technology		CPL qualified debug store
Intel Virtualization		Debug store
Turbo Boost		Debugging extensions
Enhanced SpeedStep		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Process context identifiers
		Self-snoop
		TSC rate is ensured to be invariant across all states
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control