Процессор для ноутбука Intel® Celeron M 560 (1M Cache, 2.13 GHz, 533 MHz FSB) SLA2D Socket P 478-pin Micro-FCPGA
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Количество товара на складе: 1 шт.
Состояние: Б/У
Гарантия: 2 мес.
Цена:
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Опрос |
Описание товара: SLA2D specifications
| General information |
| Type |
CPU / Microprocessor |
| Family |
Intel Celeron M |
| Processor number ? |
560 |
| Part number |
LF80537NE0461M
BX80537560 |
| Frequency (GHz) ? |
2.133 |
| Bus speed (MHz) ? |
533 |
| Clock multiplier ? |
16 |
| Package type |
478-pin Micro-FCPGA |
| Socket type |
Socket P |
| Architecture / Microarchitecture / Other |
| CPUID |
10661h |
| Core stepping |
A1 |
| Processor core |
Merom |
| Manufacturing technology (micron) |
0.065 |
| Number of cores |
1 |
| L2 cache size (MB) ? |
1 |
| Features |
EM64T technology ?
Execute disable bit ?
MMX
SSE
SSE2
SSE3
SSSE3 |
| Core voltage (V) ? |
1.1 - 1.25 |
| Case temperature (°C) ? |
100 |
| Thermal Design Power (Watt) ? |
31 |
| Notes on sSpec SLA2D |
- The part is discontinued. Last order date is April 16, 2010. Last shipment date for boxed processors is July 16, 2010. Last shipment date for OEM processors is October 15, 2010.
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Related S-Spec numbers
In addition to the SLA2D S-Spec, this processor was also manufactured with one pre-production S-Spec number:
NOTE: Engineering and qualifications samples are marked with this color
SLA2D CPUID information
View / search public CPUID submissions
| Intel Celeron M 560 SLA2D |
| Part number: |
LF80537NE0461M |
| Measured Frequency: |
2128 MHz |
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| Comment: |
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| Submitted by: |
CPU-World |
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General information
| Vendor: |
GenuineIntel |
| Processor name (BIOS): |
Intel(R) Celeron(R) CPU 560 @ 2.13GHz |
| Cores: |
1 |
| Logical processors: |
1 |
| Processor type: |
Original OEM Processor |
| CPUID signature: |
10661 |
| Family: |
6 (06h) |
| Model: |
22 (016h) |
| Stepping: |
1 (01h) |
| TLB/Cache details: |
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
Cache details
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
32 KB |
32 KB |
1 MB |
| Associativity: |
8-way set
associative |
8-way set
associative |
4-way set
associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
Supported instructions
| Instruction set extensions |
Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
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MONITOR/MWAIT |
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SYSENTER/SYSEXIT |
Integrated features and technologies
| Major features |
Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
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CPL qualified debug store |
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Debug store |
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Debugging extensions |
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Digital Thermal Sensor capability |
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LAHF/SAHF support in 64-bit mode |
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Machine check architecture |
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Machine check exception |
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Memory-type range registers |
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Model-specific registers |
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Page attribute table |
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Page global extension |
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Page-size extensions (4MB pages) |
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Pending break enable |
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Perfmon and Debug capability |
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Physical address extensions |
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Self-snoop |
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Thermal monitor |
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Thermal monitor 2 |
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Thermal monitor and software controlled clock facilities |
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Time stamp counter |
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Virtual 8086-mode enhancements |
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xTPR Update Control |
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