Процессор для ноутбука Intel Core 2 Duo T6600 SLGF5 Core 2 Duo T6600 (2M, 2.20GHz, 800MHz FSB) Intel® Core™2 Duo Processor T6600 (2M Cache, 2.20 GHz, 800 MHz FSB)

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SLGF5 specifications
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General information
Type    CPU / Microprocessor
Family    Intel Core 2 Duo Mobile
Processor number  ?     T6600
Part number    AW80577GG0492ML
Frequency (GHz)  ?     2.2
Bus speed (MHz)  ?     800
Clock multiplier  ?     11
Package type    478-pin micro-FCPGA
Socket type    Socket P
Architecture / Microarchitecture / Other
CPUID    01067Ah
Core stepping    R0
Processor core    Penryn-3M
Manufacturing technology (micron)    0.045
Number of cores    2
L2 cache size (MB)  ?     2
Features    EM64T technology  ? 
Enhanced SpeedStep technology  ? 
Execute disable bit  ? 
Core voltage (V)  ?     1 - 1.25
Case temperature (°C)  ?     105
Thermal Design Power (Watt)  ?     35
 
There are no notes on sSpec SLGF5

Related S-Spec numbers
In addition to the SLGF5 S-Spec, this processor was also manufactured with one production S-Spec number:
Stepping    S-Spec    AW80577GG0492MA    AW80577GG0492ML
R0    SLGF5         +
Unknown    SLGJ9    +     

SLGF5 CPUID information
View / search public CPUID submissions
Intel Core 2 Duo Mobile T6600 SLGF5
Part number:    AW80577GG0492MA
Measured Frequency:    2194 MHz
Comment:    
Submitted by:    CPU-World
 
General information
Vendor:    GenuineIntel
Processor name (BIOS):    Intel(R) Core(TM)2 Duo CPU T6600 @ 2.20GHz
Cores:    2
Logical processors:    2
Processor type:    Original OEM Processor
CPUID signature:    1067A
Family:    6 (06h)
Model:    23 (017h)
Stepping:    10 (0Ah)
TLB/Cache details:    64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache details
Cache:    L1 data    L1 instruction    L2
Size:    32 KB    32 KB    2 MB
Associativity:    8-way set
associative    8-way set
associative    8-way set
associative
Line size:    64 bytes    64 bytes    64 bytes

Supported instructions
Instruction set extensions    Additional instructions
MMX    CLFLUSH
SSE    CMOV
SSE2    CMPXCHG16B
SSE3    CMPXCHG8B
SSSE3    FXSAVE/FXRSTORE
SSE4.1    MONITOR/MWAIT
     SYSENTER/SYSEXIT
     XSAVE/XRESTORE states

Integrated features and technologies
Major features    Other features
On-chip Floating Point Unit    36-bit page-size extensions
64-bit / Intel 64    64-bit debug store
NX bit/XD-bit    Advanced programmable interrupt controller
Enhanced SpeedStep    CPL qualified debug store
     Debug store
     Debugging extensions
     Digital Thermal Sensor capability
     LAHF/SAHF support in 64-bit mode
     Machine check architecture
     Machine check exception
     Memory-type range registers
     Model-specific registers
     Page attribute table
     Page global extension
     Page-size extensions (4MB pages)
     Pending break enable
     Perfmon and Debug capability
     Physical address extensions
     Self-snoop
     Thermal monitor
     Thermal monitor 2
     Thermal monitor and software controlled clock facilities
     Time stamp counter
     Virtual 8086-mode enhancements
     xTPR Update Control
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