Процессор для ноутбука Intel Celeron 1005M 2M Cache, 1.90 GHz SR103 Разъем G2 (rPGA988B) Ivy Bridge третье поколение

SR103 specifications

General information
Type	CPU / Microprocessor
Family	Intel Mobile Celeron Dual-Core
Processor number ?	1005M
Part number	AW8063801121200
Frequency (GHz) ?	1.9
Clock multiplier ?	19
Package type	988-pin micro-FCPGA
Socket type	Socket G2 (rPGA988B)
Architecture / Microarchitecture / Other
CPUID	0306A9h
Core stepping	P0
Processor core	Ivy Bridge
Manufacturing technology (micron)	0.022
Number of cores	2
L2 cache size (KB) ?	512
L3 cache size (MB)	2
Features	EM64T technology ? Enhanced SpeedStep technology ? Execute disable bit ? MMX SSE SSE2 SSE3 SSE4 SSSE3 Virtualization technology (VT-x)
Case temperature (°C) ?	105
Thermal Design Power (Watt) ?	35
Notes on sSpec SR103
Integrated graphics controller runs at 650 MHz. The part supports DDR3-1333 and DDR3-1600 memory. The processor supports DDR3L-1333 and DDR3L-1600 memory. Frequency of integrated graphics controller in turbo mode is 1000 MHz. Direct Memory Interface speed is 5 GT/s. The OEM/tray part is discontinued. Last order date for OEM processors is Jan 23, 2015. Last shipment date for OEM processors is Jul 10, 2015.

Intel Mobile Celeron Dual-Core 1005M SR103

Part number:	AW8063801121200
Measured Frequency:	1895 MHz

Comment:
Submitted by:	CPU-World

General information

Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Celeron(R) CPU 1005M @ 1.90GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	306A9
Family:	6 (06h)
Model:	58 (03Ah)
Stepping:	9 (09h)
TLB/Cache details:	64-byte Prefetching Data TLB0: 2-MB or 4-MB pages, 4-way set associative, 32 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L2 TLB: 1-MB, 4-way set associative, 64-byte line size Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries

Cache details

Cache:	L1 data	L1 instruction	L2	L3
Size:	2 x 32 KB	2 x 32 KB	2 x 256 KB	2 MB
Associativity:	8-way set associative	8-way set associative	8-way set associative	8-way set associative
Line size:	64 bytes	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped	Inclusive Shared between all cores

Supported instructions

Integrated features and technologies

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Intel Virtualization		CPL qualified debug store
Enhanced SpeedStep		Clock modulation duty cycle extension
		Debug store
		Debugging extensions
		Digital Thermal Sensor capability
		Extended xAPIC support
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Package thermal management
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Power Limit Notification capability
		Process context identifiers
		Self-snoop
		Supervisor Mode Execution Protection
		TSC rate is ensured to be invariant across all states
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Timestamp counter deadline
		Virtual 8086-mode enhancements
		xTPR Update Control