Процессор для ноутбука Intel Core 2 Duo T7250 2.00/ 2m/M / 800 SLA49

SLA49 specifications

General information
Type	CPU / Microprocessor
Family	Intel Core 2 Duo Mobile
Processor number ?	T7250
Part number	LF80537GG0412M BX80537T7250
Processor markings	LF80537 T7250 2.00/2M/800
Frequency (GHz) ?	2
Frequency in IDA mode (GHz)	2.2
Frequency in LFM mode (GHz)	1.2
Frequency in SLFM mode (MHz)	800
Bus speed (MHz) ?	800
Clock multiplier ?	10
Package type	478-pin micro-FCPGA
Socket type	Socket P
Architecture / Microarchitecture / Other
CPUID	06FDh
Core stepping	M0
Manufacturing technology (micron)	0.065
Number of cores	2
L2 cache size (MB) ?	2
Features	EM64T technology ? Enhanced SpeedStep technology ? FSB frequency switching Intel Dynamic Acceleration Virtualization technology
Core voltage (V) ?	1.075 - 1.175
Core voltage in IDA mode (V)	1.075 - 1.25
Core voltage in LFM mode (V)	0.9375 - 1
Core voltage in SLFM mode (V)	0.8 - 0.9
Case temperature (°C) ?	100
Thermal Design Power (Watt) ?	35

There are no notes on sSpec SLA49

In addition to the SLA49 S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

Stepping	S-Spec	LF80537GG0412M	BX80537T7250
M0	QGFV	+
	QWOU	+
	SLA49	+	+
	SLAXH	+
Unknown	QELB	+

NOTE: Engineering and qualifications samples are marked with this color

Intel Core 2 Duo Mobile T7250 sla49

Part number:	LF80537GG0412M
Measured Frequency:	1995 MHz

Comment:
Submitted by:	Rodrigo

General information
Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Core(TM)2 Duo CPU T7250 @ 2.00GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	6FD
Family:	6 (06h)
Model:	15 (0Fh)
Stepping:	13 (0Dh)
TLB/Cache details:	64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache:	L1 data	L1 instruction	L2
Size:	2 x 32 KB	2 x 32 KB	2 MB
Associativity:	8-way set associative	8-way set associative	8-way set associative
Line size:	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped Shared between all cores

Instruction set extensions		Additional instructions

MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Intel Virtualization		CPL qualified debug store
Turbo Boost		Debug store
Enhanced SpeedStep		Debugging extensions
		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control